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| HSP43220/883 TM Data Sheet March 1999 FN2802.3 Decimating Digital Filter The HSP43220/883 Decimating Digital Filter is a linear phase low pass decimation filter which is optimized for filtering narrow band signals in a broad spectrum of a signal processing applications. The HSP43220/883 offers a single chip solution to signal processing application which have historically required several boards of ICs. This reduction in component count results in faster development times, as well as reduction of hardware costs. The HSP43220/883 is implemented as a two stage filter structure. As seen in the Block Diagram, the first stage is a High Order Decimation Filter (HDF) which utilizes an efficient decimation (sample rate reduction) technique to obtain decimation up to 1024 through a coarse low-pass filtering process. The HDF provides up to 96dB aliasing rejection in the signal pass band. The second stage consists of a Finite Impulse Response (FIR) decimation filter structured as a transversal FIR filter with up to 512 symmetric taps which can implement filters with sharp transition regions. The FIR can perform further decimation by up to 16 if required, while preserving the 96dB aliasing attenuation obtained by the HDF. The combined total decimation capability is 16,384. The HSP43220/883 accepts 16-bit parallel data in 2's complement format at sampling rates up to 30MSPS. It provides a 16-bit microprocessor compatible interface to simplify the task of programming and three-state outputs to allow the connection of several ICs to a common bus. The HSP43220/883 also provides the capability to bypass either the HDF or the FIR for additional flexibility. Features * This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. * Single Chip Narrow Band Filter with up to 96dB Attenuation * DC to 25.6MHz Clock Rate * 16-Bit 2's Complement Input * 20-Bit Coefficients in FIR * 24-Bit Extended Precision Output * Programmable Decimation up to a Maximum of 16,384 * Standard 16-Bit Microprocessor Interface * Filter Design Software Available DECI*MATETM Applications * Very Narrow Band Filters * Zoom Spectral Analysis * Channelized Receivers Ordering Information PART NUMBER HSP43220GM-15/883 HSP43220GM-25/883 TEMP. RANGE ( oC) -55 to 125 -55 to 125 PACKAGE 84 Ld PGA 84 Ld PGA PKG. NO. G84.A G84.A Block Diagram DECIMATION UP TO 1024 INPUT CLOCK DATA INPUT CONTROL AND COEFFICIENTS DECIMATION UP TO 16 24 DATA OUT DATA READY 16 16 HIGH ORDER DECIMATION FILTER FIR DECIMATION FILTER FIR CLOCK 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved DECIMATETM is a trademark of Intersil Corporation. IBM PC, XT, AT, PS/2TM are trademarks of IBM Corporation. HSP43220/883 Absolute Maximum Ratings Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8V Input, Output Voltage . . . . . . . . . . . . . . . . . . . GND -5V to VCC 0.5V ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Information Thermal Resistance (Typical, Note 1) JA ( oC/W) JC (oC/W) PGA Package. . . . . . . . . . . . . . . . . . . . 35 5 Maximum Package Power Dissipation at 125oC PGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.52 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC Operating Conditions Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to 5.5V Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Die Characteristics Number of Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48,250 CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS Devices Guaranteed and 100% Tested TEST CONDITIONS VCC = 5.5V VCC - 4.5V IOH = 400A, VCC = 4.5V (Note 2) IOL = 2.0mA VCC = 4.5V (Note 2) VIN = VCC or GND, VCC = 5.5V VOUT = VCC or GND, VCC = 5.5V VCC = 5.5V VCC = 4.5V VIN = VCC or GND, VCC = 5.5V, Outputs Open f = 15.0MHz, VCC = 5.5V (Note 3) (Note 4) GROUP A SUBGROUPS 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 LIMITS TEMP (oC) -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 MIN 2.2 2.6 -10 -10 3.0 TYP 0.8 0.4 +10 +10 0.8 500 UNITS V V V V A A V V A PARAMETER Logical One Input Voltage Logical Zero Input Voltage Output HIGH Voltage Output LOW Voltage Input Leakage Current Output Leakage Current Clock Input High Clock Input Low Standby Power Supply Current SYMBOL VIH VIL VOH VOL II IO VIHC VILC ICCSB Operating Power Supply Current Functional Test NOTES: ICCOP FT 1, 2, 3 7, 8 -55 TA 125 -55 TA 125 - 120 - mA 2. Interchanging of force and sense conditions is permitted. 3. Operating supply current is proportional to frequency, typical rating is 8mA/MHz. 4. Tested as follows: f = 1MHz, VIH = 2.6, VIL = 0.4, VOH 1.5V, VOL 1.5V, VIHC = 3.4V and VILC = 0.4V. 2 HSP43220/883 TABLE 2. AC ELECTRICAL PERFORMANCE SPECIFICATIONS Devices Guaranteed and 100% Tested (NOTES) (NOTE 5) GROUP A SUBGROUPS 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 -15 (15MHz) TEMP (oC) -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 MIN 66 66 26 26 0 4 TCK 8 TCK TCK +10 25 20 0 26 26 28 MAX TFIR -25 35 -25 (25.6MHz) MIN 39 39 16 16 0 4 TCK 8 TCK TCK +10 15 16 0 15 20 24 MAX TFIR -19 20 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns PARAMETER Input Clock Period FIR Clock Period Clock Pulse Width Low Clock Pulse Width High Clock Skew Between FIR_CLK and CK_IN RESET Pulse Width Low Recovery Time On RESET ASTARTIN Pulse Width Low STARTOUT Delay From CK_IN STARTIN Setup to CK _IN Setup Time on DATA_IN Hold Time on All Inputs Write Pulse Width Low Write pulse Width High Setup Time on Address Bus Before the Rising Edge of Write Setup Time on Chip Select Before the Rising Edge of Write Setup Time on Control Bus Before the Rising Edge of Write DATA_RDY Pulse Width Low DATA_OUT Delay Relative to FIR_CK DATA_RDY Valid Delay Relative to FIR_CK DATA_OUT Delay Relative to OUT_SELH Output Enable to Data Out Valid NOTES: SYMBOL t CK tFIR tSPWL tSPWH tSK tRSPW tRTRS tAST tSTOD tSTIC tSET tHOLD tWL tWH tSTADD tSTCS 9, 10, 11 -55 TA 125 28 - 24 - ns tSTCB 9, 10, 11 -55 TA 125 28 - 24 - ns tDRPWL tFIRDV tFIRDR tOUT tOEV Note 6 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 2TFIR -20 - 50 35 30 20 2TFIR -10 - 35 25 25 20 ns ns ns ns ns 5. AC Testing: VCC = 4.5V and 5.5V. Inputs are driven at 3.0V for a Logic "1" and 0.0V for a Logic "0". Input and output timing measurements are made at 1.5V for both a Logic "1" and "0". CLK is driven at 4.0V and 0V and measured at 2.0V. 6. Transition is measured at 200mV from steady state voltage with loading as specified by test load circuit and CL = 40pF. 3 HSP43220/883 TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS Devices Guaranteed and 100% Tested TEST CONDITIONS -15 (15MHz) NOTES 7, 9 7, 9 7, 9 7, 9 VCC = Open, f = 1MHz, All measurements are referenced to device GND VCC = Open, f = 1MHz, All measurements are referenced to device GND 7 TEMP (oC) -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 TA = 25oC MIN 29 29 27 2 MAX 12 -25 (25.6MHz) MIN 19 19 17 2 MAX 12 UNITS ns ns ns ns pF PARAMETER CK_IN Pulse Width Low CK_IN Pulse Width High CK_IN Setup to FIR_CK CK_IN Hold from FIR_CK Input Capacitance SYMBOL tCH1L tCH1H tCIS tCIH CIN Output Capacitance COUT 7 TA = 25oC - 10 - 10 pF Output Disable Delay Output Rise Time Output Fall Time NOTES: tOEZ tOR tOF 7, 8 7, 8 7, 8 -55 TA 125 -55 TA 125 -55 TA 125 - 20 8 8 - 20 8 8 ns ns ns 7. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design and after major process and/or design changes. 8. Loading is as specified in the test load circuit with CL = 40pF. 9. Applies only when H_BYP = 1 or H_DRATE = 0. TABLE 4. APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Test Interim Test PDA Final Test Group A Groups C and D METHOD 100%/5004 100%/5004 100% 100% Samples/5005 SUBGROUPS 1 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 7, 9 4 HSP43220/883 Burn-In Circuit HSP43220/883 TOP VIEW PINS DOWN 1 A GND START IN ASTART IN A1 2 DATA_ IN 1 START OUT VCC RESET DATA_ OUT 5 DATA_ OUT 9 DATA_ OUT 10 3 DATA_ IN 2 DATA_ IN 0 4 DATA_ IN 4 DATA_ IN 3 5 DATA_ IN 7 DATA_ IN 6 DATA_ IN 0 6 DATA_ IN 8 DATA_ IN 13 DATA_ IN 9 7 DATA_ IN 11 DATA_ IN 12 DATA_ IN 10 8 DATA_ IN 14 9 VCC 10 GND 11 GND DATA_ OUT 1 DATA_ OUT 2 DATA_ OUT 4 DATA_ OUT 7 DATA_ OUT 8 DATA_ OUT 11 B DATA_ CLK_IN IN 15 VCC DATA_ OUT 0 DATA_ OUT 3 C D E CS C_BUS 10 C_BUS 12 C_BUS 9 GND C_BUS 8 C_BUS 6 WR C_BUS 15 C_BUS 11 VCC C_BUS 7 C_BUS 5 C_BUS 3 A0 C_BUS 14 C_BUS 13 DATA_ OUT 3 VCC GND F G H DATA_ DATA_ OUT 13 OUT 12 OUT_ SELH C_BUS 4 C_BUS 2 C_BUS 1 C_BUS 0 OUT_ EMP OUT_ ENX GND FIR_ CK GND DATA_ OUT 22 DATA_ OUT 23 DATA_ DATA_ OUT 16 OUT 14 DATA_ DATA_ DATA_ OUT 19 OUT 17 OUT 15 DATA_ DATA_ DATA_ OUT 21 OUT 20 OUT 18 J K VCC DATA_ RDY L VCC BURN-IN CIRCUIT SIGNALS PIN LEAD A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 PIN NAME GND DATA_IN 1 DATA_IN 2 DATA_IN 4 DATA_IN 7 DATA_IN 8 DATA_IN 11 DATA_IN 14 V CC GND GND STARTIN STARTOUT DATA_IN 0 DATA_IN 3 DATA_IN 6 BURN-IN SIGNAL GND F2 F3 F5 F8 F1 F4 F7 VCC GND GND F15 VCC/2 F1 F4 F7 PIN LEAD C1 C2 C5 C6 C7 C10 C11 D1 D2 D10 D11 E1 E2 E3 E9 E10 PIN NAME ASTARTIN VCC DATA_IN 5 DATA_IN 9 DATA_IN 10 DATA_OUT 0 DATA_OUT 2 A1 RESET DATA_OUT 3 DATA_OUT 4 CS WR A0 DATA_OUT 5 DATA_OUT 6 BURN-IN SIGNAL F15 VCC F6 F2 F3 V CC/2 V CC/2 F14 F16 V CC/2 V CC/2 F11 F11 F13 V CC/2 V CC/2 PIN LEAD F11 G1 G2 G3 G9 G10 G11 HI H2 H10 H11 J1 J2 J5 J6 J8 PIN NAME DATA_OUT 3 C_BUS 12 C_BUS 11 C_BUS 13 DATA_OUT 10 GND DATA_OUT 11 C_BUS 9 V CC DATA_OUT 13 DATA_OUT 12 GND C_BUS 7 OUT_SEL GND FIR_CK BURN-IN SIGNAL VCC/2 F5 F4 F6 VCC/2 GND VCC/2 F2 VCC VCC/2 VCC/2 GND F8 F10 GND F0 5 HSP43220/883 BURN-IN CIRCUIT SIGNALS (CONTINUED) PIN LEAD B6 B7 B8 B9 B10 B11 K5 K6 K7 K8 K9 K10 NOTES: 10. V CC/2 (2.7 10%) used for outputs only. 11. 47k (20%) resistor connected to all pins except VCC and GND. 12. V CC = 5.5 0.5V. 13. 0.1F (minimum) capacitor between V CC and GND per position. 14. F0 = 100kHz 10%, F1 = F0/2, F2 = F1/2....F16 = F15/2, 40% - 60% duty cycle. 15. Input voltage limits: VIL = 0.8 maximum, VIH = 4.5V 10%. PIN NAME DATA_IN 13 DATA_IN 12 DATA_IN 15 CK_IN V CC DAT_OUT 1 OUT_ENP V CC GND DATA_OUT 22 DATA_OUT 19 DATA_OUT 17 BURN-IN SIGNAL F6 F5 F8 F0 VCC VCC/2 F9 VCC GND VCC/2 VCC/2 VCC/2 PIN LEAD E11 F1 F2 F3 F9 F10 K11 L1 L2 L3 L4 L5 PIN NAME DATA_OUT 7 C_BUS 10 C_BUS 15 C_BUS 14 DATA_OUT9 VCC DATA_OUT 15 C_BUS 6 C_BUS 3 C_BUS 2 C_BUS 0 OUT_ENX BURN-IN SIGNAL VCC/2 F3 F8 F7 V CC/2 VCC V CC/2 F7 F4 F3 F1 F9 PIN LEAD J10 J11 K1 K2 K3 K4 L6 L7 L8 L9 L10 L11 PIN NAME DATA_OUT 16 DATA_OUT 14 C_BUS 8 C_BUS 5 C_BUS 4 C_BUS 1 DATA_RDY V CC DATA_OUT 23 DATA_OUT 21 DATA_OUT 20 DATA_OUT 18 BURN-IN SIGNAL VCC/2 VCC/2 F1 F6 F5 F2 VCC/2 VCC VCC/2 VCC/2 VCC/2 VCC/2 Metal Topology DIE DIMENSIONS: 348 x 349.2 x 19 1 mils METALLIZATION: Type: Si - Al, or Si - Al - Cu Thickness: 8kA WORST CASE CURRENT DENSITY: 1.18 x 105A/cm2 GLASSIVATION: Type: Nitrox Thickness: 10kA All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 6 HSP43220/883 Ceramic Pin Grid Array Packages (CPGA) D S1 D1 -A- G84.A MIL-STD-1835 CMGA3-P84C (P-AC) 84 LEAD CERAMIC PIN GRID ARRAY PACKAGE INCHES SYMBOL A A1 b MIN 0.215 0.070 0.016 0.016 0.042 1.140 MAX 0.345 0.145 0.0215 0.020 0.058 0.080 1.180 MILLIMETERS MIN 5.46 1.78 0.41 0.41 1.07 28.96 MAX 8.76 3.68 0.55 0.51 1.47 2.03 29.97 NOTES 3 8 4 6 5 10 11 121 121 1 2 -B- S b1 b2 C E1 E D D1 E E1 e k L 1.000 BSC 1.140 1.180 25.4 BSC 28.96 29.97 1.000 BSC 0.100 BSC 0.008 REF 0.120 0.040 0.140 0.060 25.4 BSC 2.54 BSC 0.20 REF 3.05 1.02 3.56 1.52 C INDEX CORNER SEE NOTE 9 SEE NOTE 7 A -C- B B Q S b1 S S1 M N SECTION B-B b 0.000 BSC 0.003 11 - 0.00 BSC 0.08 Rev. 1 6/28/95 NOTES: 1. "M" represents the maximum pin matrix size. 2. "N" represents the maximum allowable number of pins. Number of pins and location of pins within the matrix is shown on the pinout listing in this data sheet. 3. Dimension "A1" includes the package body and Lid for both cavity-up and cavity-down configurations. This package is cavity up. Dimension "A1" does not include heatsinks or other attached features. 4. Standoffs are intrinsic and shall be located on the pin matrix diagonals. The seating plane is defined by the standoffs at dimensions Q. 5. Dimension "Q" applies to cavity-up configurations only. 6. All pins shall be on the 0.100 inch grid. 7. Datum C is the plane of pin to package interface for both cavity up and down configurations. 8. Pin diameter includes solder dip or custom finishes. Pin tips shall have a radius or chamfer. 9. Corner shape (chamfer, notch, radius, etc.) may vary from that shown on the drawing. The index corner shall be clearly unique. 10. Dimension "S" is measured with respect to datums A and B. 11. Dimensioning and tolerancing per ANSI Y14.5M-1982. 12. Controlling dimension: INCH. 0.008 C SEATING PLANE AT STANDOFF k A1 L e b2 Q SECTION A-A b A A O0.030 M O0.010 M C AM BM C L A1 Q |
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